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ics for communications isdn d-channel exchange controller (idec ? ) peb 2075 users manual 05.92
siemens aktiengesellschaft 2 data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about processing guidelines and quality assurance for ics, see our product overview . edition 05.92 this edition was realized using the softwaresystem framemaker ? . published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, dC8000 mnchen 80. ? siemens ag 1992. all rights reserved. as far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery, and prices please contact the offices of semiconductor group in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the type in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. peb 2075 revision history: 05.92 page subjects (changes since last revision)
peb 2075 table of contents page semiconductor group 3 05.92 1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.1 general functions and device architecture . . . . . . . . . . . . . . . . . . . . . . .15 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.4 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.1 channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.2 hdlc communication functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.4.3 collision control and switching functions . . . . . . . . . . . . . . . . . . . . . . . .33 2.4.4 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.5 preprocessed channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3 operational description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.1 microprocessor interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.4 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.5 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.1 register address layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 5 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
semiconductor group 4 05.92 p-lcc-44 p-dip-28 isdn d-channel exchange controller peb 2075 (idec ? ) cmos ic 1 features l four independent hdlc channels l 64-byte fifo storage per channel and direction l handling of basic hdlc functions flag detection/generation zero deletion/insertion crc checking/generation check for abort l address recognition l c/i channel handler l single connection and quad connection modes l iom ? interface or pcm interface l programmable time slots and channel data rates (up to 4mbit/s) l different methods of contention resolution l standard p- interface, multiplexed or non-multiplexed address and data buses l vectored interrupt l advanced cmos technology l power consumption less than 50 mw during operation. the isdn digital exchange controller peb 2075 (idec) is a serial hdlc data communication circuit with four independent channels. its telecommunication specific features make it especially suited for use in variable data rate pcm systems. in addition, the device contains sophisticated switching functions and it implements automatic contention resolution between packet data from different sources. its applications include: communication multiplexers, peripheral isdn line cards, packet handlers and x.25 packet switching devices. the idec is a fundamental building block for networks with either centralized, de-centralized or mixed signaling/packet data handling architectures. type version ordering code package peb 2075-n v.1.3 q67100-h6189 p-lcc-44 (smd) peb 2075-p v.1.3 q67100-h6188 p-dip-28
semiconductor group 5 1.1 pin configuration (top view) features itp00727 sd3x sd2r 1 10 9 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 12 11 25 26 27 28 sd0x 2075 peb 13 14 16 15 sd1r sd1x dd v v ss dcl fsc res ale int tsc idec wr cdr cs sd0r sd3r sd2x ad3 ad2 ad ad0 rd 4 ad 5 ad 6 ad 7 ad r itp03527 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 29 30 31 32 33 34 35 36 37 38 39 7 8 9 10 11 12 13 14 15 16 17 rd/ds wr/r/w a2 dcl a1 a0 fsc res ale cs n.c. int n.c. cdr n.c. sd1x sd1r sd0x n.c. n.c. sd0r sd2x sd2r sd3x n.c. sd3r a6 n.c. ad7 ad6 n.c. ad5 ad4 a5 ad2 a4 ad1 ad0 a3 n.c. idec 2075 ss v tsc dd v ad3 peb r p-lcc-44 p-dip-28 idec ? peb 2075 idec ? peb 2075
semiconductor group 6 features 1.2 pin definitions and functions pin definitions and functions pin no. p-lcc-44 pin no. p-dip-28 symbol input (i) output (o) open drain (od) function 4 3 1 44 42 41 39 38 3 2 1 28 27 26 25 24 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 i / o address data bus. if the multiplexed address/data m p interface bus mode is selected these lines transfer data and commands between the m p and the idec. if a demultiplexed mode is used, these lines interface with the system data bus. 13 12 9 5 2 43 35 - - - - - - - a0 a1 a2 a3 a4 a5 a6 i address bus. these inputs interface to the systems address bus to select an internal register for a read or write access. only provided in the p-lcc package and only active if a demultiplexed m p interface is selected. 17 11 cs i chip select. a low on this line selects the idec for a read/write operation. 8 8 5 - wr r/w i i write. this signal indicates a write operation, active low (siemens/intel bus mode). read/write. at "high", identifies a valid m p access as a read operation. at "low", identifies a m p access as a write operation (motorola bus mode). only provided in the p-lcc package. 7 7 4 - rd ds i i read. this signal indicates a read operation, active low (siemens/intel bus mode). data strobe. the rising edge marks the end of a valid read or write operation (motorola bus mode). only provided in the p-lcc package.
semiconductor group 7 features 16 10 ale i address latch enable. in the siemens/ intel type multiplexed m p interface mode a "high" on this line indicates an address of an internal register on the external address/data bus. in the siemens/intel type demultiplexed m p interface mode this line should be connected to v ss , in the demultiplexed motorola type m p interface mode it should be connected to v dd . 19 12 int od interrupt request. this signal is activated when the idec requests an interrupt. 15 9 res i reset. a "high" on this interrupt brings the idec into the reset state. 29 25 31 34 18 16 20 22 sd0r sd1r sd2r sd3r i serial data receive. 26 24 30 32 17 15 19 21 sd0x sd1x sd2x sd3x o serial data transmit. serial data transmit. serial data transmit. serial data transmit. serial data transmit. collision output. serial data transmit. - 11 7 dcl i data clock; supplies a clock signal either equal to or twice the data rate. 14 8 fsc i frame synchronization or data strobe signal. 22 14 tsc o time-slot control. supplies a control signal for an external driver. 21 13 cdr i collision data receive. 10 6 v ss i ground. 36 23 v dd i positive power supply. pin definitions and functions (contd) pin no. p-lcc-44 pin no. p-dip-28 symbol input (i) output (o) open drain (od) function
semiconductor group 8 features itl00726 receive cdr ad (a (r/w) wr rd (ds) int ale c sd0r sd0x cs sd1x sd1r sd2x sd2r sd3x sd3r fsc dcl tsc 5v 0v timing data collision tristate control pcm pcm/ res system 00 ... ... 6) 7 idec peb 2075 r c m r iom logic symbol
semiconductor group 9 features timing switching collision control hdlc receiver transmitter rfifo xfifo xfifo rfifo control collision switching timing xfifo rfifo xfifo rfifo serial interface logic cdr sd0x microcontroller interface dcl fsc tsc rd int 8 ad0-ad7 wr cs ale res itb00728 sd1x sd0r sd2x sd1r sd3x sd2r sd3r timing switching collision control switching collision control timing transmitter hdlc receiver transmitter hdlc receiver transmitter hdlc receiver block diagram
semiconductor group 10 features 1.3 system integration communication multiplexers the four independent serial hdlc communication channels implemented in the idec make the circuit suitable for use in communication multiplexers. the collision detection/resolution capability of the circuit allows statistical multiplexing of packets in one or several physical data communication channels, for example in dmi (mode 3) applications. centralized signaling / data packet handlers the idec can be used in central packet handlers of isdn networks to process signaling or packet data of four isdn subscribers. in this application, it may be used with or without the extended pcm interface controller (eplc ? ) peb 2055. the idec can be connected to the iom interface of the epic, which is itself connected to the pcm system highway. the epic implements concentration and time slot assignment functions. as an alternative, the idec may be directly connected to pcm highways ( figure 1 ). the size (from 1 to 8 bits) and the position of the time slot associated with each hdlc controller is software programmable. in addition to the receive and transmit data highways, the idec accepts a third input connection for collision detection purposes. the mode of collision detection is programmable. a "collision highway" (or time slot) can be used for remote collision control, as a "clear to send" lead, or for local contention resolution among several idecs.
semiconductor group 11 features figure 1 use of idec ? in central signaling / data packet handlers its00729 idec receive transmit cards line pcm highway transmit ts receive ts receive ts transmit ts pcm highway line cards r idec idec r idec r epic r transmit receive r c mm c its00730 idec transmit cards line pcm highway receive ts transmit ts pcm highway line cards r r idec idec r idec r epic transmit collision receive detect r receive collision detect collision detect ts collision detect ts transmit ts receive ts c m c m
semiconductor group 12 features line cards in de-centralized or mixed signaling / data packet handling architectures the idec can be used on peripheral line cards to process d-channel packets for isdn subscribers. the pcm controller peb 2055 has the layer-1 controlling capacity and a b-channel switching capacity for a total of 32 subscribers. the b and d channels and the control information for eight subscribers are carried by one iom interface. thus a line card dimensioned for 32-isdn subscribers may employ up to eight idecs, two for each iom connection ( figure 2 ). a high level serial communication controller (hscx) sab 82525 with two hdlc channels, or another idec may be used to transmit and receive signaling via the system highway in a common channel. again, such a common channel may be shared among several line cards, due to the statistical multiplexing capability of these controllers. in completely de-centralized d-channel processing architectures, the processing capacity of a line card is usually dimensioned so as to avoid blocking situations even under maximum conceivable d-channel traffic conditions. it may sometimes be more advantageous to perform p-packet handling in a centralized manner while keeping s-packet handling on the line cards. a statistical increase in p-packet traffic has then no effect on the line card, and can be easily dealt with by one of the modular architectures for a central packet handler shown in the previous section. a more effective sharing of the total p-packet handling capacity is the result, especially in a situation where p-packet traffic patterns vary widely from one subscriber group to another. the use of an idec in the mixed d-channel processing architecture is illustrated in figure 3 . the additional "transparent data" connections supported by the idec enable a merging of p and s packets into one d channel. possible collision situations are dealt with by the idec which uses either the additional collision detect line ( figure 3 ) or a time slot on the system highway ( figure 3 ) from the line card to the central packet handler.
semiconductor group 13 features figure 2 line card in a de-centralized d-channel handling architecture its00731 hscx / idec b s, p s, p c.c.s + c.c.p system d d s/u s/u c/i, monitor d d x8 line transceivers legend: c.c.s/p = common channel for signaling and for packed data, c/i, mon = control/indication and monitor channels for the interface respectively idec idec highways r iom c m r epic r r r r iom
semiconductor group 14 features figure 3 idec ? on a line card in a mixed d-channel processing architecture its00732 system highway coll s-p p p(s)* b b p d d line transceivers s s idec r iom r epic r c m its00733 system highway b b d d line transceivers idec s s p coll s-p +p + p(s)* + coll * s packets will be discarded by the receiver legend: p = time-slot for p packets time-slot for s packets = s coll s-p = time-slot containing information about a collision between s packets and p packets s-p r iom r epic r c m b) a)
semiconductor group 15 functional description 2 functional description 2.1 general functions and device architecture the idec is an hdlc controller which handles four hdlc communication channels, each channel fully independent and programmable by its own register set. the circuit performs the following functions: C extraction (reception) and insertion (transmission) of the hdlc data packets in a time division multiplex bit stream. C implementation of the basic hdlc functions of the layer-2 protocol, including address recognition. C interfacing of the data packets to the microprocessor bus. for the temporary storage of data packets internal flfos are used. C switching of data between serial interfaces. C implementation of different types of collision resolution. C test functions. 2.2 operating modes each hdlc controller of the idec is assigned to one time channel determined either by time slot assignment or by an external strobe signal. two basic configurations are distinguished ( figure 4 ): C in the quad connection configuration the four hdlc controllers (a - d) are connected to individual time multiplexed communication lines; C in the single connection configuration the four hdlc channels are all connected to one time multiplexed communication line. figure 4 quadconnection single connection itd00734 a b c d a b c d main connection auxiliary connections a) b) c m c m
semiconductor group 16 functional description in the quad connection configuration two modes are distinguished as follows: C each connection is a time slotted highway, the lengths and positions of the time slots are programmable (quad connection time slot mode); C each connection is a communication line, the time channels are marked by an external strobe signal (quad connection common control mode). two modes are distinguished in turn for the single connection configuration as follows: C the connection is a standard iom interface with predefined channel positions (single connection iom mode); C the connection is a time slotted highway (single connection time slot mode). for simplicity, a time slotted highway will usually be referred to as a "pcm highway", or pcm for short. table 1 four basic operation modes of the idec to program the single connection iom mode (ccr:mds1, mds0 = 10) with the slave mode (mode3-0:cms1, cms0 = 01) or with the multi master mode (mode3-0:cms1, cms0 = 10) or with the uncond. trans. mode (mode3-0:cms1, cms0 = 00) this additional programming has to be made: mode0:ccs1, ccs0 = 00 bin mode1:ccs1, ccs0 = 00 bin mode2:ccs1, ccs0 = 00 bin mode3:ccs1, ccs0 = 00 bin tsr0 = 0c hex tsr1 = 1c hex tsr2 = 2c hex tsr3 = 3c hex the four modes of operation are illustrated in figure 5 . via channel-by-channel programming, one of a number of collision detection modes may be selected in each of the basic modes of operation. for future reference, they are also depicted in figure 5 . mds1 mds0 mode description 0 0 single connection time slot mode 0 1 quad connection common control mode 1 0 single connection iom mode 1 1 quad connection time slot mode
semiconductor group 17 functional description figure 5a, 5b operating modes of the idec itc00735 a b c d collision data slave/multi-master collision mode receive transmit transmit receive transmit receive transmit receive a b c d programmable time-slots a) quad connection ts mode b) quad connection common control mode itc00736 a b c d collision data slave/multi-master collision mode receive transmit transmit receive transmit receive transmit receive strobe
semiconductor group 18 functional description figure 5c, 5c operating modes of the idec itc00737 a b c d receive transmit programmable time-slots collision data slave/multi-master collision mode bac d itc00738 a b c d receive transmit collision data slave/multi-master collision mode abcd r iom c) single connection ts mode d) single connection iom ? mode
semiconductor group 19 functional description figure 5e, 5f operating modes of the idec itc00739 a b c d receive transmit master collision mode transmit receive collision data ba c d programmable time-slots d a c b programmable time-slots itc00740 a b c d receive transmit master collision mode transmit receive collision data bac d programmable time-slots r iom e) single connection ts mode f) single connection iom ? mode
semiconductor group 20 functional description 2.3 interfaces microcontroller interface the idec is programmable over an 8-bit parallel microcontroller interface. easy and fast microprocessor access is provided by 8-bit address decoding on chip. the interface consists of 13 (19) lines and is directly compatible with processors of the multiplexed and demultiplexed address/ data bus types (siemens/intel or motorola processor families). the microprocessor interface signals are summarized in table 2 . table 2 microcontroller interface signals of the idec symbol input (i) output (o) open drain (od) function ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 i/o address data bus. if the multiplexed address/data m p interface bus mode is selected these lines transfer data and commands between the m p and the idec. if a demultiplexed mode is used, these lines interface with the system data bus. a0 ... a6 i address bus. these inputs interface to the systems address bus to select an internal register for a read or write access. only provided in the p-lcc package and only active if a demultiplexed m p interface is selected. cs i chip select. a low on this line selects the idec for a read/write operation. wr r/w i write. this signal indicates a write operation, active low (siemens/intel bus mode). read/write. at "high", identifies a valid m p access as a read operation. at "low", identifies a m p access as a write operation (motorola bus mode). only provided in the p-lcc package. rd ds i read. this signal indicates a read operation, active low (siemens/intel bus mode). data strobe. the rising edge marks the end of a valid read or write operation (motorola bus mode). only provided in the p-lcc package.
semiconductor group 21 functional description in addition to 8-bit processors, the idec supports a direct connection to 16-bit processors. thus, through an internal address transformation, it is possible to access all idec registers using either even microprocessor addresses only or odd microprocessor addresses only. serial interfaces depending on the selected mode, the idec supports four physically separate, full duplex serial interfaces, or one full duplex serial interface. in addition to the data input and data output lines, the serial interface requires a common data clock (input dcl) and a frame synchronization signal (input fsc). input data is latched on the falling edge of dcl and output data is clocked off on the rising edge of dcl. the idec may be programmed so that the data clock rate is either equal to the data rate, or twice the data rate. ale i address latch enable . in the siemens/intel type multiplexed m p interface mode a "high" on this line indicates an address of an internal register on the external address/data bus. in the siemens/intel type demultiplexed m p interface mode this line should be connected to v ss . in the demultiplexed motorola type m p interface mode it should be connected to v dd . int od interrupt request . the signal is activated when the idec requests an interrupt. res i reset . a "high" on this input brings the idec into the reset state. table 2 (contd) microcontroller interface signals of the idec symbol input (i) output (o) open drain (od) function
semiconductor group 22 functional description 2.4 individual functions 2.4.1 channel access the four hdlc controllers of the idec are connected to the serial interfaces as shown in table 3 . the table indicates the selection of the data channel, the selectable time slot widths, the output driver type, and the function of the active-low tri-state control (tsc ) output in each of the operating modes. the data output is set in a high impedance state outside the time channel where data is transmitted. od = open-drain driver, pp = push-pull driver. the output driver type refers to the sd0x (or sd0x, sd1 x, sd2x and sd3x) outputs. tsc is a push-pull signal. quad connection time-slot mode channel selection is performed via the time-slot select registers (tsr). for each hdlc channel, the 8- bit tsr register gives the position of a time slot with a two-bit resolution. the length of the time slot, either 1, 2, 7 or 8 bits, can be selected using the mode register (ccs1, 0). these parameters are common to the receive and the transmit channel. in the case where the number of bits in a pcm frame is 256 or 512, the frame synchronization signal fsc need not be provided at every pcm frame beginning, since bit counters are automatically reset at frame end. when the pcm frame length is not equal to either 256 or 512 bits, the frame synchronization signal has to be provided at the beginning of every pcm frame.
semiconductor group 23 functional description table 3 hdlc controller channel selection and characteristics od = open-drain driver, pp = push-pull driver. the output driver type refers to the sd0x (or sd0x, sd1x, sd2x and sd3x) outputs. tsc is a push-pull signal. mode channel input channel output description mds1mds0abcdabcd 0 0 sd0r sd0r sd0r sd0r sd0x sd0x sd0x sd0x single connection ts mode 0 1 sd0r sd1r sd2r sd3r sd0x sd1x sd2x sd3x quad connection common control mode 1 0 sd0r sd0r sd0r sd0r sd0x sd0x sd0x sd0x single connection iom mode 1 1 sd0r sd1r sd2r sd3r sd0x sd1x sd2x sd3x quad connection ts mode mode channel characteristics tri-state control (tsc ) signal output driver mds1 mds0 channel select channel width defined by 0 0 tsr a-d registers 1, 2, 7, 8 tsr a-d pp or od 0 1 fsc strobe arbitrary fsc inverted pp or od 1 0 fixed two-bit tss 2 fixed two-bit tss a-d od 1 1 tsr a-d registers 1, 2, 7, 8 tsr b pp or od
semiconductor group 24 functional description the tristate control output line tsc marks the time slot when data is transmitted/received by the hdlc controller b. the position of a time slot with respect to fsc, as a function of the tsr register contents, is shown in figure 6 . figure 6 position of time slot for different channel widths as a function of tsr register contents itd02723 tsr = 0 1 1 2 3 4 5 tsr = 0 2 1 2 3 4 5 7 1 2 3 4 5 8 1 2 3 4 5 fsc dcl a) 1-bit time-slot 2-bit time-slot b) c) 7-bit time-slot 8-bit time-slot d) bit bits bits bits tsr = 0 tsr = 0
semiconductor group 25 functional description quad connection common control mode channel selection is performed by an active high strobe signal provided through the fsc input. the strobe signal is common to all four hdlc channels. the tsc output is active when the fsc strobe is active. single connectionts mode the time slots selected by the tsr registers all pertain to the same pcm highway. the programming of a channel otherwise proceeds exactly as explained above. the tristate control output line tsc marks the time slots when data is transmitted/received by any of the four controllers. single connection iom - mode the iom is an interface where a frame is composed of n iom channels (n ? 1; n = 8 in figure 7 ). each iom channel has a unique structure. it consists of: two eight-bit bytes, corresponding to the isdn b channels, a monitor byte, and a control byte of which the first two bits are allocated to the isdn d channel. in the single connection iom mode the serial interface has an iom frame structure and the four hdlc channels are assigned to the d bits of four consecutive iom channels. the choice whether the four hdlc controllers are assigned to iom channels 0 - 3 or 4 - 7 is governed by the microcontroller bit vis (common configuration register). see figure 7 .
semiconductor group 26 functional description figure 7 itd03562 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch0 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b1 b2 monitor d c/i mm rx byte 1 byte 2 byte 3 byte 4 fsc dcl data in data out 125 m s r iom iom r itd03534 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 hdlc channels vis = 0 vis = 1 abcd ab d c r iom b) assignment of hdlc channels in iom ? mode a) multiplexed frame structure of the iom ? interface (n = 8)
semiconductor group 27 functional description 2.4.2 hdlc communication functions basic hdlc functions each one of the four controller channels handles the following basic hdlc functions. receive direction C flag detection a zero followed by six consecutive ones and another zero is recognized as a flag. C zero delete a zero after five consecutive ones within an hdlc frame is deleted. C address recognition a frame may be accepted or rejected on the basis of a comparison of the most significant address byte (service access point identifier sapi in link access procedure for the d- channel lapd) with three fixed sapi values. C crc checking the crc field of an hdlc frame is checked according to the generator polynomial x 16 +x 12 +x 5 +1. C check for abort seven or more consecutive ones are interpreted as an abort sequence. C check for idle fifteen or more consecutive ones are interpreted as "idle", and reported to the processor via a status bit. C minimum length checking reception of frames with less than three bytes between opening and closing flag is not reported to the microcontroller. transmit direction C flag generation a flag is generated at the beginning and at the end of every frame. C zero insert a zero is inserted after five consecutive ones within an hdlc frame. C crc generation the crc field of the transmitted frame is generated according to the generator polynomial x 16 +x 12 +x 5 +1. C abort sequence generation an hdlc frame may be terminated with an abort sequence under software control or due to a fifo underrun condition. C inter-frame time fill as inter-frame time fill either flags or idle (continuous ones) may be transmitted.
semiconductor group 28 functional description reception and transmission functions fifo structure each hdlc controller uses a 64-byte fifo per direction for the intermediate storage of data packets. all data bytes between the opening flag and the crc field of an hdlc frame are passed through the fifo. figure 8 hdlc frame structure the receive and transmit flfos are both divided, two blocks of 32 bytes each: one accessible to the microcontroller and one inaccessible to the microcontroller. while the microcontroller is reading (receive fifo) or writing (transmit fifo) data in one 32-byte block, the other block is filled (receive fifo) or emptied (transmit fifo) by the idec. thus the length of the received or transmitted frame is not limited by the fifo size. itd03535 flag crc flag generated by hdlc controller bytes passed through fifo
semiconductor group 29 functional description reception of frames address compare before a receive frame is stored, its address (the first byte following the opening flag) may optionally be compared against three fixed values. sapg "group sapi" 63 d saps "signaling sapi" 0 d sapp "packet sapi" 16 d each address compare may be individually enabled or disabled for each hdlc channel via bits ac0, 1, 2 and 3 (acr register). the effect of a match is programmable as shown in table 4 . in the table it is assumed that the address compare enable bit (ac) is set for the channel in question. if ac = 0, all valid receive frames in that channel are accepted. table 4 address compare logic scm scg scs sgp effect 0 000 001 010 011 100 101 110 111 accept all frames reject frames with sapp (16 d ) saps (0 d ) saps (0 d ) and sapp (16 d ) sapg (63 d ) sapg (63 d ) and sapp (16 d ) sapg (63 d ) and saps (0 d ) sapg (63 d ), saps (0 d ) and sapp (16 d ) 1 000 001 010 011 100 101 110 111 reject all frames accept frames with sapp (16 d ) saps (0 d ) saps (0 d ) and sapp (16 d ) sapg (63 d ) sapg (63 d ) and sapp (16 d ) sapg (63 d ) and saps (0 d ) sapg (63 d ), saps (0 d ) and sapp (16 d )
semiconductor group 30 functional description frame storage when a frame is accepted, it is stored in the receive fifo. in the case of a frame of length less than to 64 bytes, the whole frame may be stored in the receive fifo. after the first 32 bytes have been received, the device prompts the microcontroller to read data from the fifo (receive pool full rpf interrupt status). having done this, the microcontroller releases the fifo. this is done by the rmc (receive message complete) software command, after which the rest of the frame, when ready, is made available to the microcontroller ( figure 9 ). when a whole frame shorter than 32 bytes, or the final part of a frame longer than that becomes available, the condition is indicated by an rme (receive message end) interrupt status, instead of rpf. figure 9 receive fifo in the case of a frame no longer than 64 bytes. in the case of frames at least 64 bytes long, the microcontroller will repeatedly be prompted by an interrupt lo read out the fifo in blocks of 32 bytes (except possibly the final block). again, after reading a block, the microcontroller acknowledges the data by a software command and thus releases the fifo. if this is not done before an additional 32-data bytes are received, the next data byte will lead to a "data overflow" condition. in the case of several shorter frames up to seventeen may be stored inside the hdlc controller. after an interrupt (rme), one frame is available in the fifo for the microcontroller to read. up to sixteen other frames may be stored in the meanwhile in the upper half of the fifo ( figure 10 ). when the microcontroller releases the current data block from the fifo by software command, the next frame becomes available and the corresponding space is freed in the upper half for (a) subsequent frame(s) ( figure 10 ). itd03536 a) b) prior to acknowledgement after inaccessible 32 32 accessible acknowledgement block b + 1 free block b b + 1 block bytes bytes m c to to m c c m c m
semiconductor group 31 functional description figure 10 receive fifo in the case of short frames the interrupts accumulating in the process are incorporated into a queue and transferred one by one to the microcontroller as well as additional information about the frame. in particular, the frame length is stored in a register. information such as "frame aborted yes/no" and "crc error yes/no" and "data overflow yes/no", is included in an extra byte stored in the fifo after the last byte of the corresponding frame. every interrupt has to be acknowledged by the microcontroller. a full fifo at the beginning of a frame will lead to a frame overflow condition. if the microcontroller does not wish to preserve an incoming frame, the possibility exists to ignore it. when the corresponding command (rmd) is issued, the part of the frame stored is deleted and the rest of the entire frame will be ignored. itd03537 frame i + n frame i + 1 frame i + 2 frame i + n 0 < n < 16 frame i + 1 last frame i of part 32 to inaccessible bytes m c accessible to m c 32 bytes m acknowledgement prior to a) c after acknowledgement b) m c
semiconductor group 32 functional description transmission of frames 2 x 32 bytes of intermediate storage are provided per hdlc controller in the transmit direction. after up to 32 bytes have been written to the fifo, transmission is started by a software command (xhf). if the previous transmission is still underway when a new transmission command is issued, microcontroller access to the fifo will be blocked until the first transmission is completed ( figure 11 ). this means that at most one complete frame may be written to the fifo before a transmission is initiated. if a transmission request does not include a "frame end" indicator (xme), the hdlc controller will request the next data block via an interrupt if the fifo contains no more than 32 bytes. this procedure will be repeated until the microcontroller indicates that the frame is to be closed. in the case when this indication is not given and there is no more data ready for transmission, the frame is terminated with an abort sequence and the microcontroller is notified via a transmit data underrun (xdu) interrupt. the frame may also be aborted per software command. the completed transmission of an hdlc frame is reported by an xpr (transmit pool ready) interrupt status. figure 11 transmit fifo itd03538 a) b) c) prior to transmission command for frame n + 1 after transmission after interrupt "transmit pool ready" command for frame n + 1 sible frame n inacces- inacces- sible sible frame n+1 inacces- trans- mission mission trans- trans- mission frame n frame n + 1 acces- sible sible inacces- acces- frame n + 1 sible to m c to m c to m c to m c to m c to m c
semiconductor group 33 functional description 2.4.3 collision control and switching functions the idec possesses flexible collision control capabilities which are totally transparent to the microcontroller. the collision control modes enable use of the circuit in statistical multiplexing applications or in centralized or de-centralized packet switches. each of the four hdlc controllers is individually programmed in one of four modes by its own register bits cms1-0 (collision mode select). table 5 lists the four collision modes that can be selected, along with the auxiliary i/o lines used in each case. the outputs sd1 x and sd2x can be selected to be of the open-drain or of the push- pull type. table 5 collision modes of the idec cms1 cms0 description auxiliary i/o data in data out coll. in coll. out 00 01 10 11 unconditional transmission slave mode multi-master mode master mode cdr cdr cdr sd1x sd2x
semiconductor group 34 functional description unconditional transmission mode the hdlc controller transmits frames without collision detection on the transmit line (time channel). slave mode the input cdr (collision data receive) is used to control transmission of frames. this input is common to all hdlc controllers which are programmed in the slave mode. transmission is inhibited by a "low" on the cdr input. if cdr becomes "low" during the transmission of a frame, the frame is aborted by the hdlc controller, and the data output is set to high impedance. refer to figure 12 . figure 12 transmission control in the slave mode (example) note: the cdr is evaluated C at the falling edge of dcl, for a dcl rate equal to the data rate; C at the falling edge of dcl immediately preceding the rising edge used for transmission, for a dcl rate twice the data rate. the state of cdr is evaluated by the hdlc controller only in the time channel used for transmission by that controller. ( figure 12 is simplified in that the grouping of bits into time slots on sd0x ... sd3x and cdr is not depicted, i. e. bits outside the transmit time channel are not shown.) when cdr is switched high, inter-frame time fill is marked in the transmit time channel if no transmission request is pending, otherwise transmission starts at the first available instant. transmission of a previously aborted frame is automatically re-started by the hdlc controller if the beginning of the frame is still available in the transmit fifo. otherwise an interrupt (xdu) to the microcontroller indicates that the transmission has failed. itd03539 opening flag dcl single connection mode: quad connection mode: sdix, sdox cdr i = 0... 3
semiconductor group 35 functional description the slave mode is applicable in all of the basic operation modes, in both single connection and quad connection applications. however, there is only one cdr line. this should especially be noted if: C the idec is configured in the quad connection common control mode and more than one hdlc controller is operated in the slave mode; C when the same time slot is used by more than one hdlc controller in the slave mode. in both cases more than one controller is evaluating the cdr line during the same time interval, and when cdr goes "low" they all stop transmitting. multi-master mode in the multi-master mode the controllers perform a bus access procedure and collision detection in their assigned time channel(s). as a result, any number of idecs can be assigned to one physical channel, where they perform statistical multiplexing. collisions are detected by automatic comparison of each transmitted bit with the bit received via the cdr input. for this purpose a logical "and" of the bits transmitted by parallel controllers is formed and connected to the input cdr. this may be implemented most simply by defining the output line driver to be of the open drain type (ods = 1). consequently the logical "and" of the outputs is formed by simply tying them together ("wired or"). the result is returned to the cdr input of all parallel circuits. the multi-master mode is applicable in all operating modes, in both single connection and quad connection applications. in the quad connection mode, those output lines (sd0x ... sd3x) for which this collision mode is selected may be connected to cdr. the four hdlc controllers may either be programmed to transmit in separate time channels or in the same time channel. a prerequisite for the multi-master mode is that the inter-frame time fill used is "idle". the multi-master operation is as follows (refer to figure 13 ). when a mismatch between a transmitted bit and the bit on cdr is detected, the hdlc controller stops sending further data and its output is set to high impedance. as soon as it detects the transmit bus to be "idle" again, the controller automatically attempts to re- transmit its frame. by definition, the bus is assumed idle when x consecutive ones are detected in the transmit channel. normally x is equal to 8.
semiconductor group 36 functional description figure 13 collision detection in the multi-master mode (example) an automatic priority adjustment is implemented in the multimaster mode. thus, when a complete frame is successfully transmitted, x is increased to ten, and its value is restored to eight when a row of ten1s is detected on the bus (cdr). furthermore, transmission of a new frame may be started by the hdlc controller after the tenth 1. this multi-master, deterministic priority management ensures an equal right of access of every hdlc controller to the transmission medium, thereby avoiding blocking situations. master mode the master mode requires three auxiliary connections: data input cdr, data output sd1x and collision data out sd2x. this mode is applicable only in single connection operation. in the master mode, the controller performs two functions: C switching of data packets between the main connection sd0x, sd0r and the auxiliary input and output (cdr, sd1x) C resolution of collisions between data from the auxiliary connection cdr and hdlc frames from the local microcontroller. refer to figure14 . itd03450 cdr dcl or dcl 2 time interval for transmission (see note in figure 12) 3 ... 0 = i sdox sdix, quad connection mode: single connection mode: = /
semiconductor group 37 functional description figure 14 i / o connections in the master mode its02721 controller a collision control hdlc controller controller b controller c controller d programmable time-slots (tsr) sdix data out cdr data in sd2x collision out sd0x sd0r ts mode (tsr) mode fixed time-slots programmable time-slots r iom
semiconductor group 38 functional description in the ts mode the time slot programmed via the time-slot select register tsr applies simultaneously to sd0x/sd0r and to the auxiliary lines cdr, sd1x and sd2x. in the iom mode the tsr register selects a time channel on the auxiliary connections cdr, sd1x and sd2x only (however, the channel width selected should be two bits, as on the iom interface, to ensure a correct data throughput). the switching of data from sd0r to sd1x is transparent. the switching of data from cdr to sd0x depends on the state of the hdlc controller (transmit/no transmit) and on selected priorities, as follows. when no transmission command is issued to the hdlc controller, data is transparently switched through from cdr to sd0x. when a transmit request is issued but the force hdlc frame (fhf) bit is not set to 1, the data currently being received (if any) on cdr is given priority. the hdlc controller starts transmitting its frame on sd0x only after cdr is detected to be idle, in other words, when a row of eight ones is observed on cdr. simultaneously, sd2x is set "low" to indicate that no data will be accepted on cdr input data line. figure 15a shows the time relation between cdr (data in) and sd2x (collision out) as well as the logical relation between sd2x and sd0x (data out). the figures are simplified in that the grouping of bits into time slots on sd0x, and on sd2x/cdr is not depicted. when a transmit command is issued and the force hdlc frame (fhf) bit is set to 1, the frame currently being received on cdr is aborted. seven ones are appended to the last bit of the aborted frame on sd0x, after which the hdlc controller starts transmitting its frame ( figure 15b ). in both cases, sd2x is set "high" again after a delay of eight bit-times following the last "0" of the closing flag, to indicate that data is accepted on the cdr input data line. however, if a new transmit command is issued before that time, sd2x remains "low" and transmission of the new frame starts immediately after the eighth 1.
semiconductor group 39 functional description collision resolution in the master mode with programmable priority (fhf) figure 15 itd02722 xhf = 1 with 0 = fhf frame closing eight 1's cdr data collision sd2x eight bits frame from cdr frame from hdlc controller seven 1's frame sd0x data ~ ~ frame fhf = 1 with 1 = xhf flag closing flag opening flag frame closing flag flag closing frame flag opening frame from hdlc controller frame from cdr abort sequence in out out ~ ~ a) xhf command with fhf = 0 1 = xhf command with fhf b) eight bits in data cdr sd2x collision out out data sd0x 1's seven
semiconductor group 40 functional description note on data delay in master mode the data bits are switched from sd0r to sd1x and from cdr to sd0x with a minimum delay as shown in figure 16 . two different cases are distinguished: a) ts mode. in this case the time slots on sd0r/sd0x and on cdr/sd1x are identical. the data delay from cdr to sd0x is one bit, whereas the delay from sd0r to sd1 x is two bit times. iom mode with identical channel (time slot) on sd0r/sd0x and cdr/sd1x. this case is identical to the previous one. b) lom mode with a time slot on cdr/sd1x which does not coincide with the lom channel bits on sd0r/sd0x. in this case, the data bits undergo (in addition to the inherent delay due to the different bit positions) a delay of one bit time from cdr to sd0x, whereas no additional bit delay is introduced when going from sdor to sd1x.
semiconductor group 41 functional description bit delay for coinciding channel/time slot position on sd0r/sd0x and on cdr/sd1x. figure 16a bit delay from sd0r/cdr to sd1x/sd0x bit delay for non-identical channel/time slot position on sd0r/sd0x and on cdr/sd1x (possible only when sd0r/sd0x is an iom interface). figure 16b transmit delay from sd0r/cdr to sd1x/sd0x itd03530 sd0r sd0x sd1x cdr itd03531 sd0r sd0x sd1x cdr
semiconductor group 42 functional description 2.4.4 test functions a test loop is provided in each of the four hdlc controllers of the idec. when the test loop is activated, the input and the output of the hdlc channel are connected together. the test loop control is independent for each hdlc channel (bit tlp). the test loop is either transparent (forward data is outputted on the line) or non-transparent (forward data is not outputted on the line), depending on the selected mode. in the quad connection common control mode and in the single connection iom mode the loops are transparent. in the other cases they are non-transparent. during a non-transparent loop, the data output is high impedance inside the assigned time channel. 2.5 preprocessed channels the idec supports the l command/lndicate (c / l) channel at the iom-2 interface. the c/l handler takes care of the c/l channels. c/l channel handler to activate the c / i handler, ccr:cden is set to "1". the c/l handler can be used in the following switching modes: C single connection iom mode C single connection time-slot mode and in the following bus access modes: C unconditional transmission Cmaster C multi master (only 1 c / l transmitter is allowed per subscriber). in the upstream direction the signaling handler monitors the received c / l channels. upon a change C an interrupt is generated (istan:cd) C the actual value is stored in registers cir3 ... cir0. only single last look is carried out. the c/l channel is sampled in each frame. the change detection only operates on the 4-bit c/l channel. the istan:cd interrupt is cleared when istan is read. in the downstream direction the value written to cix3 ... cix0 will be sent in the c / l channels in each frame.
semiconductor group 43 operational description 3 operational description 3.1 microprocessor interface operation the idec microcontroller interface can be selected to be either of the 1. motorola type with control signals cs , r/w , ds ; address bus a0 6; data bus ad0 7 2. siemens/lntel non-multiplexed bus type with control signals cs , wr , rd ; address bus a0 6; data bus ad0 7 3. or of the siemens/lntel multiplexed address/data bus type with control signals cs , wr , rd , ale; address/data bus ad0 7 for a non-multiplexed bus including the motorola type p interface the p-lcc-44 package of the idec needs to be used, since only this package provides the additional pins for a separate 7-line address bus. the ale input is used to control the interface type as follows ale tied to v dd t (1) ale tied to v ss t (2) edge on ale t (3) the occurrence of an edge on ale, either positive or negative, at any time during the operation immediately selects interface type (3). a return to one of the other interface types is possible only if a hardware reset is issued. table 6 microcontroller interface summary 3.2 reset after a hardware reset (pin res), the configuration/command register bits are zeroed. no interrupts are active and all outputs are in a high impedance state. table 7 sums up the state of the idec immediately after a hardware reset has been applied. ale interface bus type address bus data bus control pins p-dip-28 11 5 4 p-lcc-44 17 8 7 tied to v dd tied to v ss switching motorola siemens/ intel siemens/ intel non- multiplexed non- multiplexed multiplexed a0 6 a0 6 ad0 6 ad0 7 ad0 7 ad0 7 cs wr rd cs r/w ds cs wr rd cs wr rd
semiconductor group 44 operational description table 7 state of idec after a hardware reset register name value after hardware reset (hex) meaning common registers acr ccr visr vism 00 00 00 00 address comparison disabled. single connection ts mode. interrupt vector may be read on ad bus bits 0 - 3. bits per frame: 257 to 512. bit rate is equal to clock rate. output drivers are of the push-pull type. no interrupt from any idec channel. all channel interrupts are enabled. individual registers i = a, b, c, d ista ism star cmdr mode rfbc tsr 00 00 50 00 00 00 00 no interrupts from channel i. all channel i interrupts enabled. transmit fifo is ready to be written to. receive line is idle. no commands. test loop not active. no collisions will be detected (unconditional transmission). inter-frame time fill = idle. receiver de-activated. channel i disabled (high impedance output). channel capacity is 2 bits/time slot. zero bytes received. time slot 0 selected.
semiconductor group 45 operational description 3.3 initialization the purpose of the initialization is to set the idec into a state where it is able to correctly transfer hdlc frames and to manage collisions according to the requirements of the application. the initialization process is divided into two phases. first, the common settings are determined via the registers ccr and vism. these registers determine the number of hdlc channels used, the serial interface configuration and common characteristics of the serial input/output connections ( table 8 ). table 8 initialization of idec(common bits) function register bits effect configuration serial interface characteristics interrupt configuration hdlc address recognition features ccr ccr vism ccr acr mds1-0 ods crs bns mic3-0 vis scm scg, scs, scp ac0-3 basic configuration and timing mode output driver type is open-drain or push pull clock rate = 1 or 2 x data rate number of bits per pcm frame mask any hdlc channel(s) visr may be read on ad bus bits 0-3 or 4-7 address compare mode: accept/reject selection of compare addresses address compare on/off for hdlc channel 0, 1, 2, 3
semiconductor group 46 operational description secondly, each of the hdlc channels is initialized via its own register set as shown in table 9 . the optional address comparison mode for each hdlc channel is selected by programming the acr register, located in the common address space ( table 8 ). table 9 initialization of hdlc channels (channel-per-channel) 3.4 interrupt structure special events are reported to the processor by an interrupt logic in the idec. this logic allows the connection of more than one idec to one interrupt input of a microcontroller. the interrupt structure of the idec is depicted in figure 17 . each hdlc channel of the circuit has its own interrupt status register (ista) where up to five possible interrupt causes may be read directly. when an interrupt occurs in one of the hdlc channels, the corresponding bit is set in the ista register and the interrupt line (int ) is activated. simultaneously, a bit in the vectored interrupt status register (visr) is set which indicates which of the four hdlc channels initiated the interrupt. thus, to determine the cause of an interrupt, the microcontroller performs successively a read of the visr register (address 36/3f) and a read of that ista register which was indicated by the contents of visr. function register bits effect serial interface mode tsr cms1-0 ccs1-0 tsr7-0 collision mode channel capacity time slot hdlc controller mode itf tlp cac rac inter-frame time fill pattern test loop active channel (enable receiver + transmitter, enable data outputs) activate hdlc receiver
semiconductor group 47 operational description figure 17 interrupt structure of the idec a read of the ista clears the register and deactivates the int line. the position which the four bits of the vectored interrupt status register occupy on the ad7-0 bus when the register is read, is programmable via the vectored interrupt selection bit vis (ccr register). thus, when vis = 0, the visr bits are read on ad bit positions 0-3, and when vis = 1, visr bits are read on ad bit positions 4-7. unoccupied bit positions on the bus remain in a high impedance state. the bits in visr can be selectively masked by setting the corresponding bits in the vectored interrupt status mask (vism) register to prevent one or several controllers from generating an interrupt. in that case, interrupts remain internally stored (pending) but are not displayed in the visr or ista registers. further, ista interrupts pertaining to a particular channel may be selectively masked via the interrupt status mask register of that channel. pending interrupts will cause the int line to be activated and will be reported via ista (and visr) only when the mask bits in ism (and vism) have been reset. itd03532 int. status a int. status b int. status c int. status d mask vism.visr mask ism.ista vector (4 bits) int
semiconductor group 48 operational description 3.5 processing after being initialized via the configuration/mode registers listed in tables 8 and 9 the idec is operational. the control of the data transfer is performed by commands from the microcontroller written in the command register (cmdr). events pertaining to the data transfer are reported via the interrupt status register (ista) pointed to by the vectored interrupt status register (visr). other events which do not lead to interrupts may be monitored via the status register (star) and information about the receive frames is found in the rfifo and in the receive frame byte counter (rfbc) register. the powerful fifo logic, which consists of a 2 x 32 byte receive and a 2 x 32 byte transmit fifo per channel, as well as an intelligent fifo controller, builds a flexible interface to the upper protocol layers implemented in the microcontroller. receive frame processing reception of hdlc frames with three or more bytes between the opening and closing flags is always reported to the microcontroller if address comparison is not enabled (ac = 0). if address comparison is enabled, the reception of the frame is dependent on the first byte of the received hdlc frame address field and the selected features of the address compare function ( table 4 ). all bytes between the opening flag and the crc field are stored in the rfifo. when the frame (excluding the crc field) is not longer than 31 bytes, the whole frame is transferred in one block. the reception of the frame is reported via the receive message end (rme) interrupt. the length of the frame can be read out from an 8-bit register (rfbc). a status byte is appended to the data in the rfifo after an rme interrupt. it includes information about the frame, such as frame aborted yes/no or crc valid yes/no. the frame and the status byte remain stored until the microcontroller issues an acknowledgment (receive message complete: rmc). a frame longer than 31 bytes is transferred to the microcontroller in blocks of 32 bytes plus one remainder block of length 0 to 31 bytes plus status byte. the reception of a 32-byte block is reported by a receive pool full (rpf) interrupt and the data in rfifo remains valid until this interrupt is acknowledged (rmc). this process is repeated until the reception of the remainder block reported by rme ( figure 18 ). bits 0-4 of the rfbc register represent the number of bytes stored in the rfifo, including the status byte. bits 7-5 indicate the total number of 32-byte blocks which were stored until the reception of the remainder block. bits 7-5 do not overflow when the counter status 7 has been reached and indicate in this case a message length greater than 223 bytes. the contents of the rfbc register are valid only after the occurrence of the rme interrupt, and remain valid until the microprocessor issues an acknowledgment (rmc). all receive interrupts accumulated in the meantime are stored (along with the status bytes and respective frame lengths) inside the controller and transferred one by one to the microcontroller after each rmc acknowledgment. if a frame could not be stored due to a full fifo, the microcontroller is informed of this via the receive frame overflow interrupt (rfo).
semiconductor group 49 operational description figure 18 reception of an hdlc frame transmit frame processing after checking the xfifo status by polling the transmit fifo write enable (xfw) bit or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered by the microcontroller in the xfifo. transmission of an hdlc frame is started when the transmit hdlc frame (xhf) command is issued. the hdlc controller will request another data block by an xpr interrupt if there are no more than 32 bytes in the xfifo and the frame close command bit (transmit message end xme) has not been set. when xme is set, all remaining bytes in the xfifo are transmitted, the crc field and the closing flag of the hdlc frame are appended and the controller generates a new xpr interrupt ( figure19 ). itd02720 rpf rmc (reception of 32 system t data transfer (reception of remainder) rmc rpf rmc rpf rmc rme data and status information (status byte, rfbc) transfer receiver hdlc idec bytes) bytes) (reception of 32 r c m
semiconductor group 50 operational description figure 19 transmission of an hdlc frame the microcontroller does not necessarily have to transfer a frame in blocks of 32 bytes. as a matter of fact, the sub-blocks issued by the microcontroller and separated by an xhf command, can be between 1 and 32 bytes long. if the xfifo runs out of data and the xme command bit has not been set, the frame will be terminated with an abort sequence (seven 1s) followed by inter-frame time fill, and the microcontroller will be advised by a transmit data underrun (xdu) interrupt. an hdlc frame may also be aborted by setting the transmit reset (xres) command bit. table 10 gives a summary of possible interrupts from the hdlc controller and the appropriate reaction to these interrupts. itd02718 xpr xhf xpr xhf xpr xhf xpr - xpr xhf xme idec hdlc transmitter system (transmission of flag plus 32 (transmission of 32 (transmission of remainder plus crc plus flag) t data transfer bytes) bytes) c m r
semiconductor group 51 operational description table 10 possible interrupt causes and reactions mnemonic meaning reaction rpf rme rfo xpr xdu receive pool full receive message end receive frame overflow transmit pool ready transmit data underrun read 32 bytes from rfifo and acknowledge with rmc. read rfbc4-0 bytes from rfifo and acknowledge with rmc. error report for statistical purposes (loss of a complete frame). probable cause: deficiency in software. write data bytes in the xfifo if the frame currently being transmitted is not finished or a new frame is to be transmitted, and issue an xhf (and possible xme) command. acknowledged by a read of the ista. possible causes: excessive software reaction times, or transmit data collision.
semiconductor group 52 operational description table 11 lists the most important commands which are issued by a microcontroller by setting one or several bits in the command register (cmdr). table 11 list of commands command mnemonic hex bit 7 0 meaning rmc rres rmd xhf xhfc f_xhf f_xhfc xres 80 40 20 08 0a 0c 0e 01 1000 0000 0100 0000 0010 0000 0000 1000 0000 1010 0000 1100 0000 1110 0000 0001 receive message complete. acknowledges a block (rpf) or a frame (rme) stored in the rfifo. reset hdlc receiver. the rfifo is cleared and the receiver is ready for reception. receiver message delete. the part of the frame in the rfifo is deleted and the rest of the frame will be ignored by the receiver. transmit hdlc frame. enables the transmission of the block entered last into the xfifo. the frame is not yet complete. transmit a hdlc frame and close it with crc and flag. same as preceding, but used in master mode to enforce a transmission even in the case of a collision. reset transmitter. clears the xfifo; any frame currently being transmitted is aborted.
semiconductor group 53 register description 4 detailed register description the following symbols are used throughout chapter 4 x... dont care n... not used. it has to be set to logical "0" in write accesses but may be switched by the idec to either logical level in read accesses. 4.1 register address layout the register set consists of: C one configuration register common to all four channels (ccr) C a maskable vectored interrupt status register (visr, vism) C a register for setting the hdlc address recognition mode for the four channels (acr) and, for each of the four channels, a set of individual registers. multiplexed address bus in order to support the use of a 16-bit microcontroller with multiplexed address bus, each register can be accessed with an even and an odd address value ( figure 20 ).
semiconductor group 54 register description figure 20 idec register map for a multiplexed address bus itd00741 00 channel-a register locations read write acr acr visr vism ccr ccr f 40 register locations channel-b 80 co af channel-c register locations register locations channel-d ef 2 3 d e 3 f 3 34, 37, 36, f 6
semiconductor group 55 register description the address map of the individual registers of each channel is shown in table 12 . in order to obtain the actual address of a register, a "base" has to be added to the address given in the table, as follows: base = 00 for channel a 20 for channel b 40 for channel c c0 for channel d. table 12 address map of hdlc channel registers (multiplexed address bus) address read write even odd 00 to 1f rfifo xfifo 20 29 ista ism 28 21 star cmdr 22 2b mode mode 2c 25 rfbc tsr 2a 23 cir cix
semiconductor group 56 register description non-multiplexed address bus the address layout is shown in figure 21 . the address map of the individual registers of each channel is shown in table 13 . in order to obtain the actual address of a register, a "base" has to be added to the address given in the table, as follows: base = 00 for channel a 20 for channel b 40 for channel c 60 for channel d. table 13 address map of hdlc channel registers note: the address values in the multiplexed a/d bus and non-multiplexed address bus cases are related to each other as follows. let ad0...7 be the multiplexed address bits and let a0...6 be the non-multiplexed address bits. then: a0 = ad0 exor ad3 a1 = ad1 a2 = ad2 a3 = ad4 a4 = ad5 a5 = ad6 a6 = ad7. address read write 00 to 0f rfifo xfifo 10 ista ism 11 star cmdr 12 mode mode 15 rfbc tsr 13 cir cix
semiconductor group 57 register description figure 21 idec register map for non-multiplexed address bus itd03533 00 channel-a register locations read write acr acr visr vism ccr ccr 15 1c 1d 1e 1f 20 register locations channel-b 35 40 60 55 channel-c register locations register locations channel-d 75
semiconductor group 58 register description 4.2 register description common registers common configuration register (ccr) address: 37/3e h (1f h ) read/write value after reset: 000n0000b 7 0 mds1,0 mode select vis vectored interrupt selection 0 iom channel 0 to 3 (iom mode), p data bus bits 0 to 3 for visr. 1 iom channel 4 to 7 (iom mode), p data bus bits 4 to 7 for visr. cden change detection enable. bns bit number select. 0 pcm frame is at most 256 bits long. 1 pcm frame is between 257 and 512 bits long. crs clock rate selection. 0 dcl clock rate is equal to the data rate. 1 dcl clock rate is equal to twice the data rate. ods output driver selection. 0tristate. 1 open drain. mds1 mds0 vis n cden bns crs ods mds1 mds0 description 0 0 single connection ts mode 0 1 quad connection common control mode 1 0 single connection iom mode 1 1 quad connection ts mode
semiconductor group 59 register description the ods bit selects the driver type simultaneously on all data outputs (and control output sd2x in master mode). however, in the single connection iom mode sd0x is open-drain independent of the value of ods. address compare register (acr) address: 34/3d h (1c h ) read/write value after reset: 00 h 7 0 ac0-3 address compare for channel a-d on (1) or off (0). the first byte following the opening flag of a receive frame will be compared against reference values if aci = 1 and the frame is accepted or rejected on the basis of the comparison. if aci = 0, all valid hdlc frames in that channel are stored. scm sapi compare mode 1: accept hdlc frames for which the first address byte matches selected sapi values. 0: reject hdlc frames for which the first address byte matches selected sapi values. scg sapi compare group 1: the first byte of a received hdlc frame is compared with "group sapi" sapg (63 d ). 0: the first byte of a received hdlc frame is not compared with sapg. scs sapi compare signaling 1: the first byte of a received hdlc frame is compared with "signaling sapi" saps (0 d ). 0: the first byte of a received hdlc frame is not compared with saps. scp sapi compare packet 1: the first byte of a received hdlc frame is compared with "packet sapi" sapp (16 d ). 0: the first byte of a received hdlc frame is not compared with sapp. ac3 ac2 ac1 ac0 scm scg scs scp
semiconductor group 60 register description the hdlc address compare logic is summarized in the table below. scm scg scs sgp effect 0 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 accept all frames reject frames with sapp (16 d ) saps (0 d ) saps (0 d ) and sapp (16 d ) sapg (63 d ) sapg (63 d ) and sapp (16 d ) sapg (63 d ) and saps (0 d ) sapg (63 d ) and saps (0 d ) and sapp (16 d ) 1 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 reject all frames accept frames with sapp (16 d ) saps (0 d ) saps (0 d ) and sapp (16 d ) sapg (63 d ) sapg (63 d ) and sapp (16 d ) sapg (63 d ) and saps (0 d ) sapg (63 d ) and saps (0 d ) and sapp (16 d )
semiconductor group 61 register description vectored interrupt status register (visr) address: 36/3f h (1e h ) read value after reset: xxxx0000b 7 0 or 7 0 ic0-3 interrupt from channel a-d when visr is read, these four bits are placed on the m p data bus with an offset determined by bit vis (register ccr). other bit positions on the bus remain in high impedance. mask for vectored interrupt status register (vism) address: 36/3f h (1 e h )write value after reset: nnnn0000b 7 0 mic0-3 mask for interrupt from channel a-d. the mask bits are active high. a masked interrupt is not visible when visr is read. instead, it remains internally stored (pending). any pending interrupt will be generated and the corresponding ic0-3 bit will be set when the mask bit is reset to zero. you are recommended to set bits 7-4 to 1 during write accesses. xxxxic3ic2ic1ic0 ic3 ic2 ic1 ic0 x x x x n n n n mic3 mic2 mic1 mic0
semiconductor group 62 register description individual channel registers flfos rfifo (read), xfifo (write) address: base + 00 to 1 f h (base + 00 to 0f h ) the flfos have an identical address range. all the 32 addresses give access to the current fifo location. note on rfifo the rfbc register bits 0 to 4 indicate the number of bytes currently accessible to the microcontroller in the visible 32-byte rfifo pool. if more bytes are read, the data read after "rfbc" accesses is the "old" data loaded in that part of the rfifo previous to the current data. for more than 32 accesses, the rfifo will be read cyclically (modulo 32). this will not disturb the next received frame. note on xfifo if more than 32 bytes are written to the xfifo (without a transmit command), an xdov interrupt is generated. the byte that was entered first (first byte to be sent) will be continuously overwritten by the extra write operations. when the closing flag of a receive frame is detected, a status byte is appended to the data in the rfifo. this byte has the following format: 7 0 rbc: receive byte count the length of the received frame (excluding flags and frame check sequence fcs) is n x 8 bits if rbc = 1 (n ? {1,2,3,...}). the length is not a multiple of 8 bits if rbc = 0. rdo: receive data overflow if rdo = 1, part of the frame has been lost because the receive fifo was full. crc: crc check the received fcs bytes were correct if crc = 1. rab: receive abort rab = 1 implies that the received frame was aborted. a status byte equal to a0 h indicates a correctly received frame. rbc rdo crc rab 0 0 0 0
semiconductor group 63 register description status / command registers interrupt status register (ista) address: base + 20/29 h (base + 10 h ) read value after reset: 00 h 7 0 rme receive message end. one complete frame of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the number of bytes stored is given by rfbc bits 0-4. rpf receive pool full. 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. rfo receive frame overflow. at least one complete frame was lost because no storage space was available in the rfifo. xpr transmit pool ready. one data block may be entered into the xfifo. xdu transmit data underrun. transmitted frame was terminated with an abort sequence because either 1) no data was available for transmission in xfifo and no xme command was issued, or 2) a collision has occurred after at least one block of data has been completely transmitted, and thus an automatic retransmission cannot be attempted. cd change detection interrupt. a new value has been entered into the cir register. note: it is not possible to transmit frames when an xdu interrupt remains unacknowledged. mask for interrupt status register (ism) address: base + 20/29 h (base + 10 h )write value after reset: 00 h 7 0 each interrupt source in ista register can be selectively masked by setting to "1" the corresponding bit in ism. masked interrupts are not indicated when ista is read. instead, they remain internally stored and pending. an interrupt is generated after the mask is reset to zero. rme rpf rfo xpr xdu n cd n rme rpf rfo xpr xdu n cd n
semiconductor group 64 register description status register (star) address: base + 21 /28 h (base + 11 h ) read value after reset: 50 h 7 0 xdov transmit data overflow. more than 32 bytes have been written into the xfifo. xfw transmit fifo write enable. data can be entered into the xfifo. bsy busy state on the receive line. a "0" in this bit position indicates an "idle" state on the input data line (15 or more consecutive ones). rna receive line not active. indicates whether flags/frames are being received on the line (0) or not (1). rna takes on the value "1" after seven consecutive ones are received on the line. vn3-0 version number of chip 0... a1 version 1... a2 version 2... 1.3 version xdov xfw bsy rna vn3 vn2 vn1 vn0
semiconductor group 65 register description command register (cmdr) address: base + 21/28 h (base + 11 h )write value after reset: 00 h 7 0 rmc receive message complete. reaction to rpf or rme internupt. the receive fifo pool currently accessible by the microcontroller is released for a subsequent frame (or 32-byte block of data). rres receiver reset. the hdlc receiver is reset, the receive fifo is cleared of any data. rmd receive message delete. reaction to rpf or rme interrupt. the entire frame is to be ignored by the receiver. the part of the frame already stored is discarded. xhf transmit hdlc frame. transmission of an hdlc frame (or of a block thereof) is initiated. fhf force hdlc frame. used in the master collision mode (cms1,0 = 11). when this bit is set and a transmit hdlc frame (xhf) command is issued, the controller aborts the frame from cdr (if any) by sending seven 1s on sd0x and then starts transmission. sd2x is set "low" to indicate that no data will be accepted on cdr input data line. xme transmit message end. indicates that the current transmit frame is to be closed with crc and flag. xres transmitter reset. the hdlc transmitter is reset, xfifo is cleared of any data and the hdlc frame currently being transmitted (if any) is aborted. rmc rres rmd x xhf fhf xme xres
semiconductor group 66 register description mode register (mode) address: base + 22/2b h (base + 12 h ) read/write value after reset: 00 h 7 0 tlp test loop input and output of hdlc channel are connected together when tlp = 1. the test loop is either transparent (if mds1,0 = 01, 10) or not (if mds1,0 = 00, 11). cms1,0 collision mode select. itf interframe time fill idle (itf = 0) or flags (itf = 1 ) are used as interframe time fill. rac receiver active. receiver is activated (1 ) or deactivated (0). cac channel active. a channel is completely disabled (receiver and transmitter are inactive, transmit line is high impedance, no tsc is output) as long as cac is "0". ccs1,0 channel capacity select. these bits select the number of bits in the time slot where data are received and transmitted. they have a significance only when mds1,0 = 00 or 11 (single connection ts mode and quad connection ts mode). the bit rates given below assume a channel repetition rate of 8 khz. tlp cms1 cms0 itf rac cac ccs1 ccs0 cms1 cms0 description 0 0 1 1 0 1 0 1 unconditional transmission slave mode multi-master mode master mode ccs1 ccs0 time - slot width channel data rate 0 0 1 1 0 1 0 1 2 bits 1 bit 8 bits 7 bits 16 kbit/s 8 kbit/s 64 kbit/s 56 kbit/s
semiconductor group 67 register description command/lndicate channel receive channel 0 - 3 (cir0 - 3) (read) address: 23,2a + offset (multiplexed), 13 + offset (demux) reset value: nnnn1111 b bit 7 bit 0 bit7: not used. bit6: not used. bit5: not used. bit4: not used. ci3-0: received c/i code, will be updated in each frame. ci3 is the bit received first. command/lndicate channel receive channel 0 - 3 (cix0 - 3) (write) address: 23,2a + offset (multiplexed), 13 + offset (demux) reset value: nnnn1111 b bit 7 bit 0 bit7: not used. bit6: not used. bit5: not used. bit4: not used. ci3-0: received c/i code, will be updated in each frame. ci3 is the bit received first. nnnnci3ci2ci1ci0 nnnnci3ci2ci1ci0
semiconductor group 68 register description recelve frame byte counter (rfbc) address: base + 25/2c h (base + 15 h ) read value after reset: 00 h 7 0 rdc7-0 receive data count total number of bytes of received frame, including the status byte. the contents of the register are valid after an rme interrupt. rdc4-0 indicate the length of the data block currently available in the receive fifo. rdc7-5 count the number of full 32-byte blocks of a frame which have already been received. if the frame length exceeds 223 bytes, rdc7-5 hold the value "111", only rdc4-0 continue to count modulo 32. time-slot register (tsr) address: base + 25/2c h (base + 15 h )write value after reset: 00 h 7 0 ts7-0 time-slot select determine the particular time slot where the hdlc controller is to receive and transmit. this register has a significance only when mds1,0 = 00,10 or 11 (single connection modes and quad connection ts mode). the register gives the position of a time slot (either 1, 2, 7 or 8 bits wide, cf. ccs1,0) in two-bit increments (two-bit resolution). the position of the time slot is relative to a frame sync signal that marks the beginning of a pcm frame. rdc7 rdc6 rdc5 rdc4 rdc3 rdc2 rdc1 rdc0 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0
semiconductor group 69 5 electrical characteristics absolute maximum ratings parameter symbol limit values unit ambient temperature under bias t a 0 to 70 c storage temperature t stg C 65 to 125 c voltage on any pin with respect to ground v s C 0.4 to v dd + 0.4 v dc characteristics t a = 0 to 70 c; v dd = 5 v 5 %, v ss =0 v parameter symbol limit values unit test condition min. max. l-input voltage v il C0.4 0.8 v h-input voltage v ih 2.0 v cc +0.4 v l-output voltage v ol 0.45 v i ol = 7 ma (sd0xsd3x) i ol = 2 ma (all other pins) h-output voltage h-output voltage v oh v oh 2.4 v dd C0.5 v i oh = C 400 m a i oh = C 100 m a power supply current operational i cc 10 ma v dd =5 v, dcl = 4096 khz inputs at 0 v/ v dd , no output loads power down 1 ma input leakage current output leakage current i li i lo +10 m a0 v< v in < v dd to 0 v 0 v < v out < v dd to 0 v capacitances t a =25 c; v dd = 5 v 5 %, v ss =0 v parameter symbol limit values unit test condition min. max. input capacitance c in 510pf i/o capacitance c io 10 20 pf electrical characteristics
semiconductor group 70 electrical characteristics ac characteristics t a = 0 to 70 c, v dd =5v5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and at 0.8 v for a logical "0". the ac testing input/output waveforms are shown below. figure 22 input/output waveforms for ac tests its00621 = 150 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf
semiconductor group 71 electrical characteristics microcontroller interface timingmp read cycle siemens/intel bus modemp read cyclemp read cyclemp read cycle figure 23 figure 24 figure 25 itt00712 rd x cs ad0 - ad7 t rd data t df rr tt ri m p read cycle itt00713 wr x cs ad0 -ad7 t dw data t wd ww tt wi m p write cycle itt00714 wr x cs ad0 - ad7 t la cs x rd or address ale t als t al t aa t ad multiplexed address timing
semiconductor group 72 electrical characteristics figure 26 motorola bus mode figure 27 itt00715 wr x cs a0 - a5 t ah t as address cs x rd or non - multiplexed address timing itt00716 cs x ds d0 - d7 t rd data t df dsd t rr t t ri r/w t rwd m p read cycle
semiconductor group 73 electrical characteristics figure 28 figure 29 itt00717 cs x ds ad0 - ad7 t dw data t wd dsd t ww tt wi r/w rwd t m p write cycle itt00718 cs x ds ad0 t ah t as - ad5 address timing
semiconductor group 74 electrical characteristics interface timing parameter symbol limit values unit min. max. ale pulse width t aa 50 ns address setup time to ale t al 20 ns address hold time from ale t la 35 ns address latch setup time to wr , rd t als 35 ns address setup time t as 10 ns address hold time t ah 25 ns ale guard time t ad 15 ns rd delay after wr setup t dsd 0ns rd pulse width t rr 120 ns data output delay from rd t rd 120 ns data float from rd t df 25 ns rd control interval t ri 75 ns wr pulse width t ww 60 ns data setup time to wr x cs t dw 30 ns data hold time from wr x cs t wd 10 ns wr control interval t wi 70 ns
semiconductor group 75 electrical characteristics serial interface timing dcl characteristics figure 30 definition of dcl period and width parameter symbol limit values unit test condition min. typ. dcl period t p 230 160 ns ns single clock rate double clock rate dcl high t wh 90 50 ns ns single clock rate double clock rate dcl low t wl 70 ns itt00744 t wh wl t t p 2.0 v v 0.8
semiconductor group 76 electrical characteristics input/output characteristics fsc in single connection modes and quad connection in ts mode figure 31 fsc timing characteristics itd00745 dcl equal to data rate rate 1st bit of frame of frame bit 2nd 1st bit of frame 2nd bit of frame 1st bit of frame t fh t fs t fh t fs t odd t odf t odd t idh t ids t idh t ids t odd t odf t odd t idh t ids data out data in data in data out rate twice the equal to dcl rate data dcl fsc 1st of frame bit
semiconductor group 77 electrical characteristics fsc timing characteristics *note: this delay is applicable in two cases when the first time slot has been programmed: 1) when fsc appears for the first time, e.g. at system power-up. 2) when the number of bits in the pcm frame is not equal to either 256 or 512. parameter symbol limit values unit min. max. fsc set-up time t fs 60 ns fsc setup time* t fs2 110 fsc hold time t fh 30 ns output data delay from dcl t odd 60 ns input data set-up t ids 25 ns input data hold t idh 20 ns output data delay from fsc* t odf 160 ns
semiconductor group 78 electrical characteristics fsc in quad connection common control mode figure 32 fsc characteristics (strobe) parameter symbol limit values unit min. max. fsc set-up time t fs1 60 ns fsc hold time t fh1 30 ns output data from high impedance to active t ozd 80 ns output data from active to high impedance t odz 40 ns output data delay from dcl t odd 60 ns input data set up t ids 25 ns input data hold t idh 20 ns itd00746 t fs1 t ids t idh t odd t ozd t ozd t fh1 t fh1 high impedance high impedance dcl fsc data data out in
semiconductor group 79 electrical characteristics figure 33 data i/o characteristics data out: sd0x in single connection modes sd0x, sd1x, sd2x, sd3x in quad connection modes sd1x, sd2x in master mode data in: sd0r in single connection mode sd0r, sd1x, sd2r, sd3r in quad connection modes cdr in slave, multi-master and master modes res characteristics parameter symbol limit values unit min. max. output data delay from dcl t odd 60 ns input data set-up t ids 25 ns input data hold t idh 20 ns tsc delay from dcl t tcd 60 ns parameter symbol limit values unit min. max. res high t rwl 16 x t p ns itd00747 t ids t idh t odd dcl data out data in tsc t tcd
semiconductor group 80 6 appendix 1. the version number (star0-3:vn1, vn0) has been incremented to 10 bin. 2. idec version a3 has a c/i channel handler implemented. if ccr:bit3 is set to 0 in all write accesses as specified in the idec technical manual for version a1 and a2, upward compability is ensured. when ccr:bit3 is programmed to 1, the c/i channel handler is active. to support the c/i channel handler, these changes have been made: ista0-3:bit1 change detection interrupt (maskable, reset when the appropriate ista is read). please refer to idec c/i channel handling 2/90 for details. register address (multiplexed busses) address (separate busses) reset value access cir0 cir1 cir2 cir3 cix0 cix1 cix2 cix3 23,2a hex 63,6a hex a3,aa hex e3,ea hex 23,2a hex 63,6a hex a3,aa hex e3,ea hex 13 hex 33 hex 53 hex 73 hex 13 hex 33 hex 53 hex 73 hex xf hex xf hex xf hex xf hex xf hex xf hex xf hex xf hex rd rd rd rd wr wr wr wr appendix
semiconductor group 81 7 package outlines 35.9 1 14 15 28 -0.4 2.54 0.45 1.5 1.5 0.25 14 15.24 +0.1 -0.3 +1.2 0.5 3.5 4.6 0.3 +0.1 0.25 15.24 0.2 index marking max max min max plastic dual-in-line package, p-dip-28 dimensions in mm plastic-leaded chip carrier, p-lcc-44 (smd) smd = surface mounted device package outlines

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